A BIT-SERIAL ARCHITECTURE FOR A MULTIPLIERLESS DCT

Abstract

This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For lower power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. Varying data word length, MSE obtained from our approach and some similar algorithms are also investigated and reported.